PURPOSE: To provide the method and device which control a bus in a data processing system.
CONSTITUTION: These method and device are provided with a first control bit (SAA*), a second control bit (CLA*), and at least one end signal (TA*, TRA*, TE*). The CLA* signal is an input to a main master 10. An external base address is given to the main master 10 so that a slave device can access the base address. The CLA* signal is asserted by the slave device to indicate that the base address to give plural addresses from the main master 10 are circulated in the unit of bits, and each of these addresses is derived from the internal base address of the main master 10. Generally, four addresses are given through the internal control of the main master for each base address in response to three successive assertions of the CLA* signal.
RONARUDO DABURIYUU SUTENSU
JIEFUAASON ERU GOKINGO
JIYON PII HANSEN
