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Title:
DATA PROCESSING SYSTEM AND MAIN MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPH05342098
Kind Code:
A
Abstract:

PURPOSE: To make block access to the clown order of addresses similar to the block access in the up order at the data processing system and main memory controller for a vector computer or the like.

CONSTITUTION: In the case or performing access from a data processing unit 19 to the data of continuous addresses on plural main storage devices 18 in the clown order, the block access in the down order is detected in a main memory controller 10 and by modifying the access request address, the access request address is translated to an address corresponding to the access request address of the block access in the up order. Thus, data related to the block access in the down order can be transferred between each main storage device 18 and each data processing unit 19.


Inventors:
SEKI TSUYOSHI
Application Number:
JP1992000150240
Publication Date:
December 24, 1993
Filing Date:
June 10, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/06; G06F12/00; G06F12/02; G06F15/16; G06F15/177; G06F17/16; (IPC1-7): G06F12/06; G06F15/16; G06F15/347
Attorney, Agent or Firm:
小笠原 吉義 (外2名)



 
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