PURPOSE: To simplify hardware constitution without improving the processing speed of a CPU by executing the reading of a reproduced time code and the control of data output timing with the same CPU.
CONSTITUTION: A buffer memory 61 controls the output timing of the parallel data of 16 bits to a terminal 62 in order to compensate a part, in which the time mismatching of reproduced data from two types of decode data can not be mechanically compensated. The timing control of writing and reading in the memory 61 is executed by supplying the reproduced time code to a host computer with a CPU64 and receiving the command of output time control. Further, the CPU64 executes the giving and receiving of the data with a clock generator 56 for the formation of the time code. However, since the CPU64 executes processing at a low speed in comparison with a CPU for the correlative arithmetic of a correlation device, the high speed processing is not requested. Accordingly, since the exclusive CPU is not provided, a data processing system is simplified even in the hardware constitution.
YAMASHITA NOBUITSU
NAGASAWA KENICHI
