PURPOSE: To read out instruction words in the extended space by a program counter of no capacity, by causing the processor itself to store instruction words of an instruction group other than the normal instruction group in the extended address and to address instruction words by the address smaller than the extended address.
CONSTITUTION: Locations 0W64kW of the memory are used as basic address space 28, and locations 64W128kW are used as extended address space 29, and control program 30, decoding program 31, and a part of the beginning of object program 32 are stored in space 28. Program 32 is stored in space 29, and this program 32 is described with OI instructions 33 other than instructions of the data processor. These instructions 33 are decoded by decoding program 31 to make it possible that the processor itself executes them, and instruction words are addressed by the address smaller than the extended address and can be read out by the program counter.
YAMAMOTO JIYUNICHI
YAMAGISHI MASATO
HASEGAWA SAKAE
DOUMEN NOBUYOSHI
