PURPOSE: To improve the efficiency of utilization of main memory device MM by performing cancellation among CPUs through a device connected to respective CPUs via individual interface lines in an information processor equipped with CPUs and main memory device MM.

CONSTITUTION: A plural number of CPUs 00W0n are connected to MMs 10W1n respectively. Through interface lines between the both, signals required direct for the writing and reading operation of MM are transmitted. Respective CPUs are connected to cancellation device 20 by IF lines 30W3N consisting of up and down lines. When CPU 00 sends a write request to one of MMs, the request is sent via the corresponding IF line and at the same time, a cancellation request signal and write address at that time are sent to device 20 via IF line 30. Then, device 20 sends the address and cancellation request signals, sent via IF line 30, to other CPUs, except CPU 00, via IF lines 31W3N and each CPU cancels information stored in its buffer memories on the basis of the address.