To improve performance by reducing access latency at the time of accessing a peripheral module, such as data readout, being connected to a low-speed bus, from a CPU, etc. connected to a high-speed bus.
A data processing unit includes a CPU bus 40 for connecting a CPU 41 and a RAM 42, a peripheral bus 50 for connecting one or more peripheral modules 51, a bus bridge controller 1 connected to the respective buses for signal synchronization processing between the buses, a clock generator 30 for supplying a clock signal to each module, a set section 20 for setting a value indicating timing determined by the signal on the peripheral bus 50 and supplying the set value to the bus bridge controller 1 as a timing signal. When accessing the peripheral module 51 from the CPU 41, the bus bridge controller 1 retains data of the peripheral bus 50 at the timing according to the above timing signal, and transfers the retained data to the CPU bus 40.
| JPH08255142 | PARALLEL PROCESSOR DEVICE |
| WO/2018/212818 | USB POWER CONTROL ANALOG SUBSYSTEM ARCHITECTURE |
YAMADA HIROMICHI
KATAOKA TAKESHI
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