DATA PROCESSOR AND LOGICAL ARITHMETIC UNIT

Japanese Patent JP3819872

B2

PROBLEM TO BE SOLVED: To provide a data processor capable of keeping the power consumption constant irrespective of the content of data to be a computation object.
SOLUTION: When the state of two signal lines I1, I2 on the input side or two signal lines O1, O2 on the output side is (1, 0), the data are defined as 1-bit data having a value 1, and when the state is (0, 1), the data are defined as 1-bit data having a value 0. Register 1, 2 input the 1-bit data expressed by (1, 0) or (0, 1) when a CTLR signal is in a state of high in accordance with a CLK signal and and temporarily hold it, and output the 1-bit data expressed by (1, 0) or (0, 1) which has been held. When the CTLR signal is in the state of low, invalid data expressed by (0, 0) are provided, but the register 1, 2 do not take in the invalid data. At this time, the invalid data (0, 0) are outputted by AND circuits 6, 7.

Koichi Fujisaki

JP2003146491A

September 13, 2006

May 23, 2003

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Toshiba Corporation

H03K19/20; H04L9/10; G09C1/00; G11C5/06; H03K19/00; (IPC1-7): G09C1/00; H03K19/20

JP2000332597A

WO1999067766A1

Tiri, K., Akmal, M., Verbauwhede, I.,A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differe,Proceedings of the 28th European Solid-State Circuits Conference 2002(ESSCIRC 2002),2002年 9月24日,p.403-406
松原裕之,渡邊孝博,中村維男,暗号VLSIプロセッサのための固有電力消費アーキテクチャ,情報処理学会論文誌,2001年 4月15日,第42巻 第4号,p.950-957
Tiri, K.,Publications and Presentations ,2006年 5月16日,URL,http://www.ee.ucla.edu/~tiri/db75.html

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto

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