To enable a data cache memory to independently prefetch or write data back at initial setting by an arithmetic control unit by previously reading much data needed for arithmetic processing in the data cache memory in quantities independently of the arithmetic control unit.

The data cache memory 4 of the data processor 1 temporarily holds the data needed to execute an instruction fetched by the arithmetic control unit 2, and stores data of plural words and effective address information common to them in plural storage areas 20, 21, and 22 of the data cache memory 4 so that they correspond to each other. Then 1st cache control parts 34 and 24 holds certain data, utilized for the instruction execution of the arithmetic control unit 2, in the storage areas 20, 21, and 22 so that they can be used again, and a 2nd cache control part 25 holds the data in the storage areas 20, 21, and 22 according to control information initially set by the instruction execution of the arithmetic control unit.