Title:
DATA PROCESSOR PROVIDED WITH SAVING AND RELOADING FUNCTION FOR REGISTER
Document Type and Number:
Japanese Patent JP3154748
Kind Code:
B2
Abstract:
PURPOSE: To save and reload data to and from the register at a high speed without providing an instruction execution device with any dedicated hardware which causes the limitation of an operation frequency or an increase in circuit scale.
CONSTITUTION: The instruction generation device 5 when inputting a 2nd control signal indicating that an instruction showing the saving and reloading of plural registers is detected generates plural saving/reloading instructions for a single register and outputs them to an instruction saving device 4. An instruction decoding device 2 decodes plural instructions supplied from an instruction fetch device 1 and the instruction saving device 4 at the same time to output resources that the decoded instructions use to an interference detection device 6 and also inputs the inputs the generation state of data dependence relation from the interference detection device 6 to output a control signal corresponding to the instruction whose data dependence relation is not detected as a 1st control signal and the instruction whose the dependence relation is detected to the instruction saving device 4 while outputting a 2nd control signal when the instruction showing the saving and loading of the registers is detected.
Inventors:
Kiyohara, Tokuzo
Application Number:
JP17501791A
Publication Date:
April 09, 2001
Filing Date:
July 16, 1991
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F9/42; G06F9/38; G06F9/46; G06F9/48; (IPC1-7): G06F9/42
Attorney, Agent or Firm:
中島 司朗