Title:
DATA PROCESSOR PROVIDING BUFFER MEMORY
Document Type and Number:
Japanese Patent JP3734578
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To miniaturize a buffer memory while considering system performance by resetting the writing pointer of a specified buffer memory which is provided between the writing circuit and the reading circuit of a packet to zero at the time or starting the packet.
SOLUTION: The tuner 1 of a digital television decoder obtains a baseband- modulated signal, demodulates it by a demodulator/error corrector 2, corrects an error and writes it in a synchronous memory 3 having FIFO(first-in first-out) stack structure. A demultiplexer 4 executes control by a microcontroller 5. Here, a synchronous memory 3 is provided between the demodulator/error corrector 2 writing data packet with length L in the synchronous memory 3 and the demultiplexer 4 reading the packet from the synchronous memory 3 and the writing pointer of the synchronous memory 3 is reset to zero at the time of starting the packet. Moreover, when n expressed an integer more than two, the measure of the synchronous memory coincides with L/n which is rounded off to be the succeeding integer.
Inventors:
Sharaf Anna
Albert Dorner
Etienction
Albert Dorner
Etienction
Application Number:
JP29552096A
Publication Date:
January 11, 2006
Filing Date:
November 07, 1996
Export Citation:
Assignee:
THOMSON multimedia S.A.
International Classes:
G06F5/06; H04L13/08; G11C7/00; H04N7/08; H04N7/081; H04N7/26; H04N7/32; (IPC1-7): H04L13/08; G06F5/06; G11C7/00; H04N7/08; H04N7/081; H04N7/24
Domestic Patent References:
| JP5219133A | ||||
| JP64050649A | ||||
| JP62177647A | ||||
| JP3265324A | ||||
| JP8032543A | ||||
| JP7038444A | ||||
| JP2501436B2 | ||||
| JP6069913A |
Attorney, Agent or Firm:
Tadahiko Ito