PURPOSE: To execute the transfer processing of data at high speed by separating the buses of a memory and CPU and transferring data between the memory and an input or output means in parallel to the operation of CPU since the buses of the memory and the input or output means can be connected.
CONSTITUTION: When MPU 1 accesses RAM 3, a data selector 101 and an address selector 102 select the buses IND and INA of MPU 1 and respectively connects them to the buses MD and MA of RAM 3. When MPU 1 accesses ROM 2 or I/O 5 on the other hand, the buses IND and INA and MPU 1 are separated from the buses MD and MA of RAM 3. Namely, the data selector 101 connects the data bus MD of RAM 3 to the data bus IFD or IMD and the address selector 102 connects the address bus MA to the address bus IFA or BM. Thus, RAM 3 can store input data from an interface 4 and outputs recording data 9 to a recording head 9, namely, it can execute a parallel processing in a period when MPU 1 accesses ROM 2 or the I/O port 5.
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MASUKI KAZUYUKI
