PURPOSE: To reduce the number of flip-flops for a synchronizing circuit by synchronizing an asynchronous board block provided for each board with a system bus clock and driving a digital circuit inside the present board corresponding to this synchronized board clock.

CONSTITUTION: An asynchronous board clock 102 of an intra-board oscillation circuit 21 is supplied to a delay circuit 201 and the asynchronous board clock delayed for plural stages is connected to a selector 202. Next, an asynchronous board clock 103 selected by the selector 202 is frequency-divided by a frequency divider circuit 203 and compared with a system bus clock 101 by a phase comparator 204. Thus, the asynchronous board clock 102 is synchronized with the system bus clock 101 and the synchronous board clock 103 is generated. Therefore, even when the flip-flop performs synchronization in one-stage configuration, in such a system, the set-up time or hold time of the flip-flop can be satisfied.