PURPOSE: To write data in the 2nd operand address through minimum processing means by providing the titled device with the 1st and the 2nd operand address exchanging function.

CONSTITUTION: When an address exchange specifying function is specified, the contents of the 1st operand address delay register 540 and the 2nd operand address delay register 520 are inputted to the 2nd operand address register 420 and the 1st operand address register 440 respectively and the contents of the 1st and 2nd operand address registers which are specified before one machine cycle are exchanged mutually. Consequently data can be written in the 2nd operand address by the three stages of procedures consisting of the exchange of the 1st and the 2nd operand addresses, writing by the 2nd operand address, i.e., the contents of the 1st operand address register 440 and reexchange of the 1st and the 2nd operand addresses.