PURPOSE: To prevent the erroneous reading of data written by a CPU from one port of a dual port memory due to the change of the processing time of a CPU of the data readout circuit where the multiplex processing part of a PCM terminal equipment reads out data from the other port at regular intervals.

CONSTITUTION: The circuit is provided with a dual port memory 42 one port of which is connected to a CPU 41, a control circuit 43 connected to the other port of the dual port memory 42, and a temporary storage memory connected to the CPU 41 and the dual port memory 42. The highest order address of the dual port memory 42 is connected to be reverse logic in the right and left ports, connected to a synchronizing signal line feeding a synchronizing signal to the CPU 41 from the circuit 43, the output data of the CPU 41 is temporarily stored in the temporary storage memory 11, synchronized with the synchronizing signal to be transferred from a temporary storage memory 11 to the dual port memory 42.