To eliminate missing of data and to reduce the power consumption, even when a data transmission speed is changed greatly.

This data reception circuit is provided with an AT command/ start bit width detection/sample clock generating section 1, that measures only a bit width of a start bit of a specific character placed at the head of a series of serial data by using a reception clock, automatically recognizes the data transfer speed of a series of the serial data, frequency-divides the received clock at a frequency division value corresponding to the recognized data transfer speed to generate a baud rate clock and generates one sample clock by each prescribed number of the baud rate clocks, and the reception circuit samples a series of the serial data by the sample clock.