PURPOSE: To prevent a decrease in the processing speed when lots of data are processed by discriminating presence of new data from a 1st register circuit in an output of a 2nd register circuit so as to clear data latched in each register circuit.
CONSTITUTION: The register is made up of a register circuit 1 for data set, a register circuit 2 for data read, an AND circuit receiving an output of the circuit 2 as a 1st input and a read request signal from a read request source as a 2nd input, and a mask signal generating circuit 3 controlling a timing of receiving new data by the register circuit 2 and holding the reception of new data by the register circuit 2 based on a read request signal from a read request source. Whether or not new data from the register circuit 1 are included in an output from the register circuit 2 is discriminated and when included, data latched in the register circuits 1, 2 are cleared and when not included, a clear signal generating circuit 4 clears data only latched in the register circuit 2.
NARITA SATOSHI
HAYASHI TOMOYUKI
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