Title:
DATA REPRODUCTION DEVICE
Document Type and Number:
Japanese Patent JPH1198462
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To read both a PI series and a PO series at a high speed even in the case of using a DRAM by mapping data in a memory so that data after demodulation are read from each of pluralities of memory banks in the unit of a prescribed data amount. SOLUTION: It is required to store data from a data input circuit 7 to a memory at once for error correction. In this case, an address conversion circuit 5 converts a 1st address signal generated by an address generating circuit 4 into a 2nd address signal. Furthermore, the circuit 5 outputs a bank switching signal to allocate data in the memory to select a bank for each PI series in the order of the PI series. Thus, the PI series has consecutive addresses of the same bank and then is read at a high speed by selecting a long burst length. Furthermore, the PO series has discontinuous addresses, but since the same bank is not employed for the PO series, data are read at a high speed by selecting the bank at error correction.
Inventors:
HIRABAYASHI MASAYUKI
NAGAI YUTAKA
TAKEUCHI TOSHIFUMI
NAGAI YUTAKA
TAKEUCHI TOSHIFUMI
Application Number:
JP25464597A
Publication Date:
April 09, 1999
Filing Date:
September 19, 1997
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H04N5/92; G06F11/10; G11B20/10; G11B20/18; G11C7/10; G11C7/24; H03M13/00; H03M13/29; (IPC1-7): H04N5/92; G11B20/18
Attorney, Agent or Firm:
Ogawa Katsuo
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