PURPOSE: To reduce the current consumption in a shift register by constituting a data shift circuit to stop switching operation of a circuit not contributing to data shift.

CONSTITUTION: In the shift register, a clock control circuit 6A is provided on a first stage, and DFF circuits 41-43 of continuous three stages are provided on the poststage, and another clock control circuit 6B is provided on the poststage, and the DFF circuits 44-47 of continuous four stages are provided on the poststage. The clock control circuits 6A, 6B are provided with a clock input terminal 61, an enable terminal 62, a feedback terminal 63, a reset terminal 64 and a clock output terminal 65. Then, this circuit is constituted so that the supply of a clock signal to the DFF circuit operating no data shift is stopped. Thus, only an FF circuit of a group corresponding to the clock control circuit outputting the clock signal performs the switching operation, and no FF circuits of other group perform the switching operation since the supply of the clock signal is stopped by the corresponding clock control circuits.