PURPOSE: To read data in an optional direction regardless of a reduction rate by dividing the data into blocks, sampling and grouping data in each block, and storing in plural memories which operate in parallel.

CONSTITUTION: Input data is inputted to an S/P shift register 2 and converted into an 8-bit parallel signal, which is shifted cyclically by a shift register 2 and then stored in a memory circuit 4 through a latch 3. The memory circuit 4 consists of either memories M1WM8 capable of operating independently of one another. The data is divided into blocks, and data in the same row and the same column in each block are sampled at intervals of specific bits; and the results are stored in the memories M1WM8 while grouped. Data from the memory circuit 4 is outputted through a shift register 5, data converting circuit 6, P/S shift register 7, and selector 8.