PURPOSE: To reduce the burden on the processing of software by fetching at least data in a digital signal only during the period from the end of a control clock to the start of the following control clock and sending out this data only during the period from the start to the end of the control clock.
CONSTITUTION: A signal of the high level is outputted to the Q output terminal of an RS flip flop FF 80 until a signal of the high level, namely, an end detection signal (waveform (c)) is supplied to the reset terminal R to re set the RS FF 80 after a signal of the high level, namely, the AND signal between a start detection signal (waveform (d)) and data (waveform (e)) is supplied to the set terminal S to set the RS FF 80, and said signal of the high level outputted to the Q output terminal is supplied to the other input terminal of an AND circuit 81. Consequently, data (waveform (e)) of the high level is sent if this data is supplied to one input terminal of an AND circuit 76. Thus, data is taken in from a decoder only in the data fetching period of the control clock supplied from a microprocessor, and data is sent to the microprocessor only in the data sending-out period.
OKUBO HIDEAKI
YAMASHITA MITSUYOSHI
