PURPOSE: To prevent the fetch of erroneous data by a high speed clock system during the transition period of the data by stopping the output of a chip select signal to a register at least in one high speed clock cycle before and after the output of a command to the high speed clock system.
CONSTITUTION: At the time of loading the data from a data line 104 by a measurement H/W 2(high speed clock system), a chip select signal(cs) inputted from a microprocessor 1 (low speed clock system) to a register 3 is masked by a mask circuit 50 at least in one clock cycle period of a CLK 2 before and after a load signal. Thus, the new data can be prevented from being written in the register 3 in the period. Then, the writing of the new data in the register 3 and the output of the new data to the data line 104 are operated during that time, and the H/W 2 fetches the new data based on the load signal after the completion of the transition from the old data to the new data.
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KIISU UINDOMIRAA
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