PURPOSE: To make the data transfer high-speed, by providing a counter which outputs false address data and switching selectively the output of the counter and address data to access a main storage device.

CONSTITUTION: In case of the data transfer from an input/output device C5 to a storage device C3, a microprocessor MPU is always set to the read mode. High- order bits of the address are inputted to a control circuit C2 from the MPU, and the circuit C2 detects the transfer mode to close a gate G1 and open a gate G2. Next, the MPU outputs start address data of the storage device C3 onto a data bus B2, and this data is taken into a counter C4 and is inputted to the storage device C3 through the gate G2. Meanwhile, stored data from the input/output device C5 is outputted onto the bus B2. A write command is given from the control circuit C2 to the storage device C3 by a signal C3CTL. Thus, the first data is supplied to the storage device C3.