PURPOSE: To decrease the data transfer time by using a means to perform simultaneously the output and input processing actions for transfer of data and to control the data transfer so as to avoid the overlap between output or input processing actions.
CONSTITUTION: The initialization signal IRST is applied to NOR circuits 407 and 410 as well as an NOT circuit 413 respectively to initialize flip-flop circuits 403W406. Each JK type flip-flop circuit is initialized. Then a transfer start signal REQ0 is supplied from an input terminal 4003 while a clock signal CLK is supplied from an input terminal 4002. Thus a data output processing action out of an external circuit (1)2 is carried out continuously together with an input processing action of said output data to an external circuit (2)3. At the time, the control is given so as to avoid the overlap between the data input processing action and a new data output processing action.
JPS4953342A | 1974-05-23 | |||
JPS5759243A | 1982-04-09 | |||
JPS5312241A | 1978-02-03 |