PURPOSE: To perform efficient data transfer without conciousness of an opposite device and queuing by providing a data transfer control circuit capable of controlling independently input/output.

CONSTITUTION: A first-in first-out (FIFO) memory 100 capable of independently controlling input/output, is provided on the input side. In addition, an FIFO300, capable of independently controlling input/output, is provided on the output side. A main memory 200 for temporary storage of transferred data is provided between the FIFO100 and FIFO300. A selector 700 selects a read address or write address from address counters 500 and 600, and supplies the address to the main memory 200. A write control 400 fetches data from the FIFO100 on the input side and controls writing into the main memory 200. A write control 900 reads data from the main memory 200, and controls writing into the FIFO300 on the output side.