PURPOSE: To lighten the burden of a CPU, and also to increase its processing speed, by constituting an address controlling circuit for designating an address of a memory, of a hardware circuit, and reducing the software processing of the CPU.

CONSTITUTION: This device is provided with the first address controlling means for controlling an address of the first memory 21, and the second address controlling means for controlling an address of the second memory 22. When the first address data and a readout instruction signal are provided to the first address control means from a CPU, the first address controlling means designates an address corresponding to the first memory 21, reads out data, and transfers this data to an accumulator 11 in the CPU. On the other hand, when the second address data and a write instruction signal are provided from the CPU1, the second address controlling means designates an address corresponding to the second memory 22, and writes data stored in the accumulator 11.