Title:
DATA TRANSFER CONTROLLER
Document Type and Number:
Japanese Patent JP3515142
Kind Code:
B2
Abstract:
PURPOSE: To provide a data transfer controller capable of executing much continuous data transfer without reducing the performance of a CPU.
CONSTITUTION: This data transfer controller is constituted of an interface 102 with an external storage device 103, an interface 104 with a buffer memory 105, a data transfer interface to a data processor, and an arbitration means for an access to the memory 105. Consequently the system performance of a multimedium equipment, a TV game equipment, etc., requiring much data transfer can be improved. In addition, the size and price of the system can be reduced. A slow speed CPU can be also used. Data distribution to an equipment such as the TV game equipment in which a display period and a non- display period periodically appear and an equipment requiring data non- periodically can be efficiently executed.
Inventors:
Ishida, Takuya
Application Number:
JP15786993A
Publication Date:
April 05, 2004
Filing Date:
June 03, 1993
Export Citation:
Assignee:
SEIKO EPSON CORP
HUDSON SOFT CO LTD
HUDSON SOFT CO LTD
International Classes:
G06F13/12; G06F13/18; H04B14/00; (IPC1-7): G06F13/12
Attorney, Agent or Firm:
石井 康夫
石井 康夫 (外1名)
石井 康夫 (外1名)
Previous Patent: AGENT FOR PREVENTING ASCITES OF BROILER AND METHOD FOR PREVENTING ASCITES
Next Patent: PATTERN ADDITION AND REGISTRATION DEVICE
Next Patent: PATTERN ADDITION AND REGISTRATION DEVICE