PURPOSE: To minimize the bus arbitration time necessary to acquire again after a bus is once released in a DMA control.

CONSTITUTION: By a clock counter 102, the time from a bus use request output to a central processing unit until obtaining a bus control right is measured, and by a clock counter 103, the time from when the bus control right is acquired until the transfer request from a connection peripheral device is negated is measured, and a transfer counter 109 counts the number of transfer data during that. A transfer rate counting circuit 106 counts a data transfer rate from the above-mentioned counting time and the number of the transfer data, and a pulse generating circuit 107 generates the transfer control pulse approximate to the counting data transfer rate. Thus, the unnecessary bus arbitration action time in a peripheral device can be reduced and the transfer efficiency can be improved.