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Title:
DATA TRANSFER DISPLAY SYSTEM
Document Type and Number:
Japanese Patent JPS60138658
Kind Code:
A
Abstract:

PURPOSE: To attain confirmation of a data transfer process state in a data transfer mode by providing an up/down counter and updating and displaying successively the data transfer process information in response to the transfer of data.

CONSTITUTION: An up/down counter 22 which stores the data transfer state is connected to a CPU13. An up/down action is designated to the counter 22 by an FF1. For this FF1, an up-signal Up and a down-signal Down are supplied to a set terminal S and a reset terminal R respectively from the CPU13. While a clock is supplied to the counter 22 from the CPU13 via an AND circuit 23. The gate of the circuit 23 is controlled by the output of an FF2. When the data is transferred between a magnetic tape MT21 and the CPU13, the count value of the counter 22 is decreased. At the same time, the data transfer process information is updated successively via the FF1, 2, etc. and then displayed to a display circuit 15. Thus it is possible to confirm the data transfer process state in a data transfer mode.


Inventors:
OGATA JIYUNJI
Application Number:
JP24640783A
Publication Date:
July 23, 1985
Filing Date:
December 27, 1983
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
H04L29/12; G06F3/153; G06F13/00; G06F13/38; (IPC1-7): G06F3/14; G06F13/00; H04L13/00
Attorney, Agent or Firm:
Takehiko Suzue



 
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