DATA TRANSFER MEMORY DEVICE - 富士通株式会社

Title:

DATA TRANSFER MEMORY DEVICE

Document Type and Number:

Japanese Patent JP3832947

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To transfer a variety of data to CU, etc., at high speed without a break by generating a data output enable signal, based on a clock which is generated by means of a memory device, etc., in a prescribed position.
SOLUTION: A plurality of memory devices 3-1 to m are provided with return clock input output means 1-1 to m for inputting/outputting a return clock RCLK which is generated, based on a main clock MCLK outputted from a data processing part 4. In this case, the clock RCLK is generated by the input/output means 1-m which is placed in the farthest position from the processing part 4 and the data output enable signal DQE is generated from the output activating means 2-1 to m of the optional devices 3-1 to m. The signal DQE is synchronized with the clock RCLK and permitted to flow toward the processing part 4. Therefore, data transfer is enabled to the processing part 4 in the same access time even when system bus length becomes long and also data transfer is executed at higher speed.

Inventors:

Yasuhiro Fujii

Application Number:

JP31392797A

Publication Date:

October 11, 2006

Filing Date:

November 14, 1997

Export Citation:

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