PURPOSE: To provide a method and system for improving the efficiency of data transfer of a data processing system.
CONSTITUTION: Each of many processors 10 has an attached buffer for storing data transferred through a common bus 8. The common bus 8 connects the processors and memories to each other. Each processor 10 continuously monitors the common bus during a specific period after another processor tries to perform operation and can send a selected control signal when the tried operation nearly contravenes data coherence in the data processing system. When the control signal is sent onto the common bus, data transfer from the buffer to the processor is inhibited. When the control signal is not sent out onto the common bus, the data transfer from the buffer to the processor is allowed.
MOORE CHARLES R (US)
REESE ROBERT J (US)
JPH02281356A | 1990-11-19 | |||
JPH02230345A | 1990-09-12 |
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