PURPOSE: To make data transfer in a memory directly in high speed possible, by splitting a memory having a longer characteristic than an access time at least into two units as for the memory cycle.

CONSTITUTION: The system consists of a memory section 4 which makes data write/read according to the state of a memory selection signal SEL given from a control section 3 by taking an output of an adder 2 adding an offset signal and a memory address designation as a real address and a memory write signal WR, and a memory section 5 which is directly accessed with the same memory address designation and makes write/read of data according to the state of a signal SEL2 given from a CPU and a memory write signal WR'. For example, in reading out of data in the address A of the memory section 5, memory elements having longer memory access time than the memory cycle time are used as the memory sections 4 and 5, and the readout data is written in the memory section 4 before one memory cycle is finished.