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Patent Searching and Data


Title:
DATA TRANSFER SYSTEM
Document Type and Number:
Japanese Patent JPS58217040
Kind Code:
A
Abstract:

PURPOSE: To shorten a data processing time, by transferring data to a data processor in parallel every time the number of bits of converted data reaches a specific value, and detecting a start mark.

CONSTITUTION: Data read by a reader in bit series is sent through a data line 3 to a serial-parallel converter 1, where it is converted into parallel data in response to a clock signal from a clock signal line 2. When the number of bits of the parallel data reaches, for example, eight, a counter 6 sends an output signal to a 8-bit latch/bus driver 4 to be sent out to a data bus 5. A latch circuit 7, on the other hand, is set by the output signal of the counter 6 and an interruption signal is sent to a CPU. Thus, no start mark detecting circuit is used, so the amount of hardware is reduced and data is processed at a high speed because of the parallel processing.


Inventors:
SHINTANI TETSUHIKO
Application Number:
JP9968982A
Publication Date:
December 16, 1983
Filing Date:
June 10, 1982
Export Citation:
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Assignee:
FUJITSU KIDEN
International Classes:
H03M9/00; G06F3/08; G06F13/00; G06K7/00; (IPC1-7): G06F3/00; G06F3/04; G06F5/04; G06K7/016
Domestic Patent References:
JPS5640946A1981-04-17
JPS54124944A1979-09-28
Attorney, Agent or Firm:
Yoshiyuki Osuge (1 outside)