Title:
DATA TRANSMISSION SYSTEM AND COMMUNICATION CONTROLLER
Document Type and Number:
Japanese Patent JP3127523
Kind Code:
B2
Abstract:
PURPOSE: To shorten the transmission delay time in which transmission data passes in a communication controller for connection of a computer to a network.
CONSTITUTION: A direct memory controller (DMAC) 40 in a communication controller 2 is provided with a means which makes an interim report at an arbitrary timing designated by a local processor 70. The local processor 70 is provided with a means which calculates the timing, when under-run does not occur during data transmission to a network 3, based on the difference between the speed of data transfer from a main memory 20 in a computer 1 to a buffer memory 50 and the network transmission speed, a means which gives this timing to the DMAC 40 as the interim report timing, and a means which synchronizes the completion of protocol processing and the interim report from the DMAC 40 to start a memory controller (MAC) LSI 60. Thus, data transmission to the network is started before a one-packet portion of data to be sent to the network is completely transferred from the main memory in the computer to the buffer memory in the communication controller.
Inventors:
Tatsuya Yokoyama
Tetsuhiko Hirata
Mika Mizutani
Tetsuhiko Hirata
Mika Mizutani
Application Number:
JP28597591A
Publication Date:
January 29, 2001
Filing Date:
October 31, 1991
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F13/00; G06F13/38; H04L13/08; H04L47/56; (IPC1-7): H04L12/56; G06F13/00; H04L13/08
Domestic Patent References:
| JP63310247A | ||||
| JP6247241A | ||||
| JP6482837A | ||||
| JP4233352A | ||||
| JP358543A | ||||
| JP63308447A | ||||
| JP3192937A |
Attorney, Agent or Firm:
Yasuo Sakuta