Title:
DATA TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JPH0897803
Kind Code:
A
Abstract:
PURPOSE: To prevent malfunctions in a reception part at the time of the transmission/reception control of data through a buffer memory.
CONSTITUTION: A transmission part is provided with a parity check circuit 10 and a logical data conversion circuit 11 and the parity check of a transmission buffer memory 1 is performed. When a parity error is present, signals inside a transmission frame are converted in the logical data conversion circuit 11, a transmission frame format is changed to an erroneous format, the frame is cancelled as a CRC error on a reception part side and the data contents of the erroneous frame are prevented from being transmitted to the reception part.
Inventors:
SHIKADA HIROTAKA
Application Number:
JP22934194A
Publication Date:
April 12, 1996
Filing Date:
September 26, 1994
Export Citation:
Assignee:
NIPPON ELECTRIC ENG
International Classes:
H04L1/00; (IPC1-7): H04L1/00
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)