To eliminate a jump of a count value due to deviation of a clock oscillation circuit by providing a reception node which controls a read of pieces of data according to clocked time data on a part corresponding to the clocked time of a 1st clock as to synchronized clocked time data.

When a crystal oscillator in a transmission-side node 10 oscillates at a frequency a little higher than that of a crystal oscillator in a reception-side node 20, the counting operation of an internal cycle time counter 53 is gradually delayed and the count value becomes smaller than the value of cycle start data X. Namely, delay is caused. The value of the counter 53 should be extracted at a point 326.00 of time, but extracted at a point 325.75 of time. At the point of time, the counter 53 is rewritten to 326.00, and counted up thereafter corresponding to the clock of the internal crystal oscillator. The value of a cycle time register 54 is one clock faster than the internal clock, but the advance is absorbed by the operation of a clock generating circuit 23. Further, an advance is also adjusted as well.