Title:
DATA WARRANT CIRCUIT
Document Type and Number:
Japanese Patent JPH08181611
Kind Code:
A
Abstract:
PURPOSE: To surely process digital data in plural bits independently of a transmission speed of data.
CONSTITUTION: Digital data in plural bits sent in the unit of bytes are latched by a data latch section 2. It is monitored that digital full bits of digital data are confirmed to be arranged by the data latch section 2 and when all bits are arranged, the data latch section 2 sends the digital data to a D/A converter section 1 based on a control signal sent through a control line. Thus, even when transmission interval of digital data in the unit of bytes is extended because of a slow data transmission speed, analog data are surely outputted from the D/A converter section 1 without missing or error in the digital data.
Inventors:
OMORI TAKESHI
Application Number:
JP32104294A
Publication Date:
July 12, 1996
Filing Date:
December 22, 1994
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
G06F13/42; H03M1/08; H03M1/66; (IPC1-7): H03M1/08; H03M1/66
Attorney, Agent or Firm:
Ishida Chochichi (2 outside)
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