Title:
DC BOOSTING DEVICE
Document Type and Number:
Japanese Patent JPS56136175
Kind Code:
A
Abstract:
PURPOSE:To reduce power loss of a transistor at ON-OFF time, by providing a capacitor between an absorbing inductor, which has primary winding and secondary winding, and 2 diodes and a transistor. CONSTITUTION:When the transistor 3 is conducted, current IC (broken line) which passes into the transistor 3 is controlled by the absorbing inductor 12, and collector voltage VC (broken line) drops rapidly reducing the power loss. Electromagnetic energy which is accumulated in the absorbing inductor 12 charged the capacitor 15 to the level of load-side voltage. When the transistor 3 is nonconducted, because the current at that time of recovery of the transistor 3 passes through the capacitor 15, collector voltage VC of the transistor 3 is unable to rise rapidly, and therefore, power loss of the transistor 3 can be reduced. When the transistor 3 became completely nonconducted, the electromagnetic energy having been accumulated in the absorbing inductor 12 is efficiently supplied to a load 6 through diodes 13 and 14.
Inventors:
FUKUDA MAMORU
Application Number:
JP3895580A
Publication Date:
October 24, 1981
Filing Date:
March 28, 1980
Export Citation:
Assignee:
FUTABA KOGYOSHO KK
International Classes:
H02M3/155; (IPC1-7): H02M3/155