Title:
DC TRANSMISSION RATE CORRECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3720884
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a DC transmission rate correction circuit in which processing of Y signal without waveform distortion is conducted.
SOLUTION: An output voltage is limited to an APL limiter circuit 7 from an output result of an APL detection circuit 6. When an APL amount exceeds a prescribed value, the prescribed voltage is fed to a DC transmission rate correction circuit 2, and when the APL is a prescribed level or below, a voltage in response to the APL amount is outputted. The DC transmission rate correction circuit 2 corrects the luminance signal based on the voltage receiving the limit.
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Inventors:
Hideo Matsuo
Application Number:
JP27289195A
Publication Date:
November 30, 2005
Filing Date:
October 20, 1995
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Digital Media Engineering Co., Ltd.
Toshiba Digital Media Engineering Co., Ltd.
International Classes:
H04N5/16; (IPC1-7): H04N5/16
Domestic Patent References:
| JP60048675A | ||||
| JP52055321A | ||||
| JP5115018A | ||||
| JP61184056A | ||||
| JP3159374A | ||||
| JP5030386A | ||||
| JP5336407A | ||||
| JP7154644A | ||||
| JP7154646A | ||||
| JP7212619A |
Attorney, Agent or Firm:
Susumu Ito
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