Title:
DE-INTERLEAVING DEVICE
Document Type and Number:
Japanese Patent JP3295372
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the device scale of a de-interleaving device and to simplify constitution.
SOLUTION: One word is composed of 32 bits and one block is composed of 32 words. Interleaved data obtained by sequentially and circularly dividing one block into four phases at every word by exchanging a bit column and a word column are written into RAM 01 for one block. The output of higher five bits and the output of lower five bits in a counter 02 are exchanged and used whenever data of one block is written as signals designating the higher address and the lower address of five bits in RAM 01. Data is read from the designated address one bit by one and data of the next block is written into the address which is read by one bit by one. At the time of exchanging, higher two bits are shifted to the side of the lower bit against the output of higher five bits and the output of lower five bits, and the bits are rearranged. Only RAM 01 is used, and the restoration of the word column and the bit column and phase separation are executed. Then, a device scale can be reduced and constitution can be simplified.
Inventors:
Hiroyuki Kasai
Application Number:
JP11213398A
Publication Date:
June 24, 2002
Filing Date:
April 22, 1998
Export Citation:
Assignee:
Japan Precision Circuits Co., Ltd.
International Classes:
H03K9/00; H03M13/27; (IPC1-7): H03M13/27
Domestic Patent References:
| JP5815353A | ||||
| JP63128820A | ||||
| JP760413B2 |
Attorney, Agent or Firm:
Kazuko Matsuda