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Title:
DEBUG DEVICE OF MULTIPROCESSOR
Document Type and Number:
Japanese Patent JPS598068
Kind Code:
A
Abstract:

PURPOSE: To ensure an effective debugging with a simple constitution, by setting conditions for each processor to be debugged, detecting the state of a processor coincident with said conditions and supplying the result of the above-mentioned detection to other processors.

CONSTITUTION: Both processors 20 and 30 to be debugged set previously specific addresses respectively. The processor 20 executes a start instruction to the processor 30. As a result, the state of the processor 30 at the starting side is traced when a POST macroinstruction is executed by another processor 30 at a shift register 60-1. While the processing route is traced when the processor 20 gives start at a shift register 60-2. Thus a debugging is possible for both processors 20 and 30.


Inventors:
OZAWA SUMIO
Application Number:
JP11573282A
Publication Date:
January 17, 1984
Filing Date:
July 02, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F11/28; G06F11/36; (IPC1-7): G06F9/06; G06F11/28
Attorney, Agent or Firm:
Toshio Nakao



 
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