Title:
DEBUG SUPPORTING DEVICE
Document Type and Number:
Japanese Patent JP2636107
Kind Code:
B2
Abstract:
PURPOSE: To efficiently observe the access of a program by inhibiting the utiliza tion of a cache memory of a processor which becomes the object of process debugging.
CONSTITUTION: A comparator 23 compares the output of a segment invalid register 22 with an access address outputted from a processor 11 and outputs its result to a cache control part 15. That is, the cache control part 15 stops the utilization of a cache memory 16 when it is shown that a trace flag register 12 is in the cource of trace and also, it is shown that the output of the comparator 23 is in a trace area. Therefore, control is executed so that an address for which the processor 11 is made access is outputted directly to a shared address line 2B and the corresponding data is fetched from a shared data line 2A. In this case, the cache control part 15 outputs the processor address of the processor 11 to a processor address line 2C and outputs a trace request to a control data line 2D.
Inventors:
YAMAMOTO AKIRA
OOHARA TERUHIKO
TAKEDA KOICHI
YAMASHITA OSAMU
OOHARA TERUHIKO
TAKEDA KOICHI
YAMASHITA OSAMU
Application Number:
JP35069191A
Publication Date:
July 30, 1997
Filing Date:
December 12, 1991
Export Citation:
Assignee:
KOGYO GIJUTSU INCHO
International Classes:
G06F9/38; G06F11/28; G06F12/08; (IPC1-7): G06F11/28; G06F9/38; G06F12/08
Domestic Patent References:
| JP3137736A | ||||
| JP282344A |
Attorney, Agent or Firm:
Hidekazu Miyoshi