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Title:
DEBUG SYSTEM
Document Type and Number:
Japanese Patent JPS6211945
Kind Code:
A
Abstract:

PURPOSE: To reduce the load of a host machine by providing a controller containing macroorder converting function which interpets a communication order and develops it to plural orders between a debug device and a device to be debugged.

CONSTITUTION: An executing order for memory reading, for example, which is produced on a host machine 2 is delivered to an interface executing software 40 from an interface executing software 20 via a standard interface 3. The software 40 develops the received order into plural orders toward a target machine 6 and sends an order to set the addresses to be read into a console 60 on the machine 6. Then the software 40 sends an order to set an order to write the addresses set on the console 61 and finally sends an order to a console 62 to read out the information given from the written address. When the communication is through between a personal computer 4 and the machine 6, the software 40 sends the results of its execution to the software 20 via the interface 3.


Inventors:
MORITA TAKAHARU
Application Number:
JP15199185A
Publication Date:
January 20, 1987
Filing Date:
July 09, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L29/08; G06F11/28; G06F13/00; H04L13/00; H04L29/00; H04L29/10; (IPC1-7): G06F11/28; G06F13/00; H04L13/00
Attorney, Agent or Firm:
Shin Uchihara



 
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