To provide a debugging system in which an expectation value comparing processing for debugging is realized at high speed by a simple operation.

In this debugging system for a system composed of a CPU 11, a memory 12, an input device 1 (13), an output device 14, a data processor 15 for processing data on the memory by a specified algorithm, a bus to be the route of the data and a direct memory access controller(DMAC) 17 for enabling memory access without the intervention of the CPU 11 for the input/ output devices and the data processor 15, the data on the memory 12 processed by the data processor 15 and an expectation value prepared on the memory are respectively read, compared and collated by the DMAC 17 and a comparing processing is broken by interruption in the case of being different from the expectation value. The need of allocating the expectation value on the memory is eliminated and memory resources and the time until starting expectation value comparison are saved.