PURPOSE: To output an arithmetic result a certain time later irrelevantly to the arithmetic result when the number of digits is determined and facilitate the design of the device, and to shorten the arithmetic speed by using a high- speed memory by multiplying decimals coded according to the binary coded decimal(BCD) system.

CONSTITUTION: This multiplier is a decimal one-digit multiplier (PL1) 1 which is composed of the memory and inputs a multiplicand An and a multiplier Bm of one digit in BCD code and outputs their product in the form of two digits of a high-order digit carry output Cn,m and a low-order digit output Mn,m in BCD code. This decimal number multiplier(MPL1) 1 consists of the memory which inputs the two inputs An and Bn as addresses and outputs the two outputs Cn,m and Mn,m as data. A programmable logic array(PLA) is usable instead of the memory. Thus, the memory or PLA is used to shorten the arithmetic time to a constant time irrelevantly to the number of digits and the need for complicated processes is eliminated by hardware and others.