To provide a decoder and a data reproducing device which is capable of correcting 1T and 2T originally impossible to be present as EFM signals, reducing the processing of an error correction circuit and improving playability.
This decoder is provided with an EFM block 12 comprising a correction part 121 for detecting the edge of binarized RF signals in a PLL asymmetry correction circuit 11, performing NRZ conversion, performing synchronization by using a clock generated in a digital PLL circuit 111, detecting 1T and 2T (T is the cycle of a channel clock) originally impossible to be present as EFM signals on a format generated at the time of performing the synchronization, correcting the signals of the detected 1T and 2T to 0 or 3T corresponding to prescribed conditions, removing 1T and 2T from the RF signals and EFM modulating the RF signals from which 1T and 2T are removed and comprising a modulation circuit 122 for EFM demodulating the signals after EFM modulation.
HASHIMOTO MINORU
KIMURA HIROMASA
