Title:
DECODER AND REPRODUCING DEVICE
Document Type and Number:
Japanese Patent JP3846771
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide flexible reproduction in slow motion not to be limited to speed divided by integer without requiring complicated circuit structure.
SOLUTION: A slow decoding control part 12b divides a reference clock generated by a VCXO 12a according to ratio of slow speed to normal speed. A STC circuit 9 counts divided clock. Start time of decoding by a MPEG video decoding part 10a is determined by comparison DTS included in a MPEG data with a count value by the STC circuit 9. A displayed time determining part 11a determines when a decoded data is outputted according to comparison between PTS included in the MPEG data and the count value by the STC circuit 9. The decoded data is stored on a frame buffer 19 temporarily and outputted in response to a signal from a determining part 16a according to information of frame frequency included the MPEG data.
Inventors:
Tetsuro Shida
Hideaki Kosaka
Hideaki Kosaka
Application Number:
JP2000190645A
Publication Date:
November 15, 2006
Filing Date:
June 26, 2000
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H04N5/92; G11B20/14; G11B27/00; H04N5/765; H04N5/783; H04N5/93; H04N5/937; H04N7/46; H04N7/50; H04N9/804; H04N19/102; H04N19/162; H04N19/172; H04N19/196; H04N19/42; H04N19/423; H04N19/44; H04N19/50; H04N19/503; H04N19/65; H04N19/89; G11B15/087; G11B15/18; (IPC1-7): H04N5/92; G11B20/14; G11B27/00; H04N5/783; H04N5/937; H04N5/93; H04N7/32
Domestic Patent References:
| JP5207420A | ||||
| JP6030379A | ||||
| JP11146339A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita
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