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Patent Searching and Data


Title:
DECODING APPARATUS AND DECODING METHOD, AS WELL AS PROGRAM
Document Type and Number:
Japanese Patent JP2004364233
Kind Code:
A
Abstract:

To decode an LDPC code so that an operating frequency can be suppressed within a sufficiently realizable range while suppressing circuit scale and memory access can be also easily controlled.

A check matrix of LDPC codes is composed of P×P unit matrixes, a matrix wherein one to several codes in one of said unit matrixes become zero, a cyclic shift thereof, a sum of a plurality of matrixes and the combination of P×P "0" matrixes. A check node calculation part 313 simultaneously operates P pieces of check nodes, and a variable node calculation part 319 simultaneously operates P pieces of variable nodes.


Inventors:
Yokogawa, Mineshi
Miyauchi, Toshiyuki
Iida, Yasuhiro
Application Number:
JP2003000294383
Publication Date:
December 24, 2004
Filing Date:
August 18, 2003
Export Citation:
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Assignee:
SONY CORP
International Classes:
G06F11/10; H03M13/11; H03M13/19; (IPC1-7): H03M13/19; G06F11/10
Attorney, Agent or Firm:
稲本 義雄