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Title:
DECODING CIRCUIT OF FACSIMILE
Document Type and Number:
Japanese Patent JPS6019360
Kind Code:
A
Abstract:

PURPOSE: To prevent duplicated write on a decoded line and also to attain high speed processing by using the constitution where a change point address of the present decoded line is loaded to the address counter of a line memory for read of the next reference line.

CONSTITUTION: A microprogram ROM27 is a memory storing a sequence of microinstruction and the microinstruction read from the microprogram ROM27 is written in the next pipeline register 28 and executed at the leading of the next clock by the control of the sequencer 26. The sequencer 26 supervises each signal of decoding line change point detection, reference line change point detection, reference line end, coded line end and decoded transmission response through a selector 24 at all times when the sequencer does not execute the operating processing, and when the sequencer 26 finds out the signal, the processor outputs the address of head address of the microprogram ROM27 to which the sequence to the signal is stored during one clock and transfers the control for the execution of sequence.


Inventors:
OOTANI NOBUHIRO
SAKURAI HIDEKAZU
Application Number:
JP12716683A
Publication Date:
January 31, 1985
Filing Date:
July 12, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H04N1/413; H04N1/417; (IPC1-7): H04N1/417
Domestic Patent References:
JPS54134919A1979-10-19
JPS57181272A1982-11-08
JPS55128967A1980-10-06
Attorney, Agent or Firm:
Yutaro Kumagai



 
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