PURPOSE: To enable the data transmission with higher transmission frequency than the band of a transmission line and to avoid the decoding mistake.

CONSTITUTION: A reception side receiving end 11 is connected to one input section of a plurality of comparators 12-0∼12-2, and different comparison reference voltages Vc0, Vc1, Vc2 are applied to another input section. The output section of the comparators is connected to a terminal D of data storage circuits 13-0∼13-2. A terminal Q of the data storage circuit is connected to the terminal D of the preceding data storage circuits 14-0∼14-2. The terminal Q of the storage circuits is connected to a digital comparator 15, where the preceding data A and the current data B are compared with every correcponding data. The outputs of A<B terminal and A>B terminal of the digital comparator 15 are respectively inputted to terminals J and K of a JK flip-flop 16, and the data readout signal obtained by inverting the clock signal at an inverter 17 is inputted to a CK terminal, allowing to pick up a compositc signal from the terminal Q.