Title:
DECODING PROCESSOR AND DECODING PROCESSING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3133677
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a decoding processor and the decoding, capable of preventing the generation of noise caused when the sum of the number of quantization bits is longer than one frame length and executing normal decoding processing.
SOLUTION: This processor is provided with a audio video data analysis section 1, a quantization bit number storage section 2, a unit frame length calculation section 3, an adder 4, a quantization bit total value storage section 5, a comparator 6, and a decoding arithmetic section 7. When the quantization bit sum is longer than one frame length, based on the comparison result in the comparator 6 in the coding arithmetic section 7, the decoding arithmetic section 7 receives an error occurrence signal 108 when the sum of quantization bits is larger than one frame length, to conduct frame interpolation with respect to the decoded and output audio video signal 109. Thus, an occurrence of noise is prevented in advance, and the decoding processing is conducted normally.
Inventors:
Osamu Kitabatake
Application Number:
JP16790196A
Publication Date:
February 13, 2001
Filing Date:
June 27, 1996
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
H04N19/00; G11B20/10; H03M7/00; H03M7/30; H04L7/00; H04L7/08; H04N5/21; H04N5/44; H04N7/52; H04N19/102; H04N19/134; H04N19/146; H04N19/166; H04N19/196; H04N19/423; H04N19/46; H04N19/59; H04N19/67; H04N19/70; H04N19/895; H04N21/43; H04N21/439; H04N21/4402; H04N21/442; (IPC1-7): H03M7/30; H04L7/08
Domestic Patent References:
| JP230284A | ||||
| JP5328135A | ||||
| JP818958A | ||||
| JP6311052A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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